1. Field of the Invention
The present invention relates generally to Digital Subscriber Line (DSL) systems and to the design of instructions for processors. More specifically, the present invention relates to a system, method and processor instruction for de-scrambling data in a DSL modem.
2. Related Art
In modems for Digital Subscriber Line (DSL) systems based on Discrete Multi-Tone (DMT) modulation, it is common to apply a data scrambling technique as part of the transmission process. For example, international and national standards for both Asymmetric Digital Subscriber Line (ADSL) and DMT-based Very High Bit-Rate DSL (VDSL) require scramblers. The stream of data bits created within the transmitter part of a DSL modem is defined by these standards to be scrambled using a specified scrambling process.
The intent of the scrambling process is to deliberately create a seemingly random pattern of bits in the scrambled output stream, even if a regular pattern of values (for example, all 0 bits, all 1 bits, or regularly alternating 0s and 1s, etc. . . . ) is received in the original input to the scrambler. This is important to avoid potential problems the presence of such patterns can cause in the subsequent generation and handling of analog signals modulated by the bit stream.
The scrambling process is, by necessity, well-defined and reversible. In a receiving modem, after the seemingly random bit sequence has been demodulated from the received analog signal, it is passed through a complementary de-scrambler which performs the inverse process and recovers the original bit stream which was fed to the scrambler in the transmitter.
In existing standards for both ADSL and VDSL, a single specification is used for the scrambling process. The effect of this scrambler specification is to create an output stream of bits y(n) (n=0, 1, 2, . . . ) from an input stream of bits x(n), in the following manner:y(n)=x(n)+y(n−18)+y(n−23)where + means addition modulo 2 (which is the equivalent to logical “exclusive-or”). Thus, the sequence of scrambled output bits depends on both the values of the unscrambled input bits x(n) and the values of previously generated (scrambled) output bits y(n).
Although the relevant DSL standards do not define the behaviour of a receiving modem, it is required in any practical receiver that the de-scrambler implements the inverse processing to create a de-scrambled sequence z(n), where n=(0, 1, 2, . . . ), by any means equivalent to:z(n)=y(n)+y(n−18)+y(n−23)where again + means addition modulo 2. If no corruption of the y(n) sequence has occurred between scrambler and de-scrambler, z(n) will equal x(n) for all n>23. For n<23, the values of both y(n) and z(n) depend respectively on the initial values of scrambler and de-scrambler versions of the sequence y(m) (m=−23, −22, . . . −1), which is not defined. If y(m) at the receiver=y(m) at the transmitter then z(n) will equal x(n) for all n>0, but this matching is neither required nor guaranteed by the standards. The fact that the first 23 bits of the de-scrambled bit stream are not reliable is usually considered an unimportant issue in practice.
In prior art hardware oriented DSL modems, the de-scrambling of data is typically performed by fixed-function logic circuits. However, such system designs are typically much less adaptable to varying application requirements. In such hardware implementations of the de-scrambling function, the data flow is fixed in an arrangement dictated by the physical movement of data through the hardware, and cannot be adapted or modified to suit different modes of use. For example, in such systems, the ‘state’ (the history of earlier input bits) is held internally within the de-scrambling hardware, rather than being passed in as and when de-scrambling is required. This means that re-using a hardware implementation to de-scramble multiple distinct data streams at the same time is either impossible, or certainly more complex to implement, since some arrangement must be made to allow the individual states for the different streams to be swapped in and out.
Current prior art DSL modems often use software to perform at least some of the various functions in a modem. One disadvantage of de-scramblers in current DSL modems is the inefficiency of such de-scramblers as the line-density and data-rates required of modems increase. As line-density and data-rates increase, so does the pressure on prior art de-scramblers to perform efficiently the individual processing tasks, such as de-scrambling, which make up the overall modem function.
Another disadvantage with current prior art de-scramblers is the software complexity required to implement such de-scramblers. Using conventional bit-wise instructions such as bit-wise shift, bit-wise excusive-or, etc. . . . may take many tens or even hundreds of cycles to perform the de-scrambling operation for a typical data block of 100 bytes.
Thus, the de-scrambling process can represent a significant proportion of the total computational cost for current prior art DSL modems, especially in the case of a multi-line system where one processor handles the operations for multiple lines. With increasing workloads, it becomes necessary to improve the efficiency of the de-scrambling of data over that of such prior art modems.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.